1 idt74fct807bt/ct fast cmos 1-to-10 clock driver commercial and industrial temperature ranges may 2010 2006 integrated device technology, inc. dsc-4242/4 c idt74fct807bt/ct commercial and industrial temperature ranges fast cmos 1-to-10 clock driver functional block diagram features: ? 0.5 micron cmos technology ? guaranteed low skew < 250ps (max.) ? very low duty cycle distortion < 350ps (max.) ? high speed: propagation delay < 2.5ns (max.) ? 100mhz operation ? ttl compatible inputs and outputs ? ttl level output voltage swings ? 1:10 fanout ? output rise and fall time < 1.5ns (max) ? low input capacitance: 4.5pf typical ? high drive: -32ma i oh , +48ma i ol ? available in qsop, ssop, and soic packages the idt logo is a registered trademark of integrated device technology, inc. description: the fct807t clock driver is built using advanced dual metal cmos technology. this low skew clock driver features 1:10 fanout, providing minimal loading on the preceding drivers. the fct807t offers low capacitance inputs with hysteresis for improved noise margins. ttl level outputs and multiple power and grounds reduce noise. the device also features -32/48ma drive capability for driving low impedance traces. in o 1 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 pin configuration qsop/ soic/ ssop top view gnd v cc gnd v cc gnd gnd v cc gnd o 5 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 in o 1 o 2 o 3 o 4 o 10 o 9 o 8 o 7 o 6
2 commercial and industrial temperature ranges idt74fct807bt/ct fast cmos 1-to-10 clock driver absolute maximum ratings (1) symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +7 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma pin description pin names description i n inputs o x outputs capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf note: 1. this parameter is measured at characterization but not tested. dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = 0c to +70c, industrial: t a = -40c to +85c, v cc = 5v 5% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level (input pins) guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (input pins) v cc = max. v i = 2.7v ? ? 1a i il input low current (input pins) v cc = max. v i = 0.5v ? ? 1a i ozh high impedance output current v cc = max. v o = 2.7v ? ? 1a i ozl (3-state output pins) v o = 0.5v ? ? 1 i i input high current v cc = max., v i = v cc (max.) ? ? 1a v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current (4) v cc = max., v o = gnd (3) ?60 ?120 ?225 ma v oh output high voltage v cc = min. i oh = ?15ma 2.4 3.3 ? v v in = v ih or v il i oh = ?32ma 2 3 ? v ol output low voltage v cc = min. i ol = 48ma ? 0.3 0.55 v v in = v ih or v il i off input/output power off leakage v cc = 0v, v in or v o 4.5v ? ? 1a v h input hysteresis for all inputs ? ? 150 ? mv i ccl quiescent power supply current v cc = max., v in = gnd or v cc ? 5 500 a i cch i ccz notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at vcc = 5v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. duration of the condition should not exceed one second. note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
3 idt74fct807bt/ct fast cmos 1-to-10 clock driver commercial and industrial temperature ranges notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i c formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f o n o ) i cc = quiescent current (i ccl , i cch and i ccz ) ? i cc = power supply current for a ttl high input (v i n = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f o = output frequency n o = number of outputs at f o all currents are in milliamps and all frequencies are in megahertz. power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. ? 0.5 2 ma ttl inputs high v in = 3.4v i ccd dynamic power supply current (3) v cc = max. v in = v cc ? 0.4 0.6 ma/mhz input toggling v in = gnd 50% duty cycle outputs open i c total power supply current (5) v cc = max. v in = v cc ? 20 30.5 (4) ma input toggling v in = gnd 50% duty cycle outputs open v in = 3.4v ? 20.3 31.3 (4) f i = 50mhz v in = gnd
4 commercial and industrial temperature ranges idt74fct807bt/ct fast cmos 1-to-10 clock driver notes: 1. see test circuits and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. t plh , t phl , t sk (t) are production tested. all other parameters guaranteed but not production tested. 4. propagation delay range indicated by min. and max. limit is due to v cc , operating temperature and process parameters. these propagation delay limits do not imply skew. switching characteristics over operating range - commercial (3,4) fct807bt fct807ct symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay 1.3 2.7 1.3 2.5 ns t phl t r output rise time ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of all banks of ? 0.5 ? 0.25 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 0.5 ? 0.35 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 0.9 ? 0.65 ns packages at same power supply voltage, temperature, package type and speed grade 50 ? to v cc /2, c l = 10pf (see figure 1) or 50 ? ac termination, c l = 10pf (see figure 2) f 100mhz outputs connected in groups of two fct807bt fct807ct symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay 1.5 3.8 1.5 3.5 ns t phl t r output rise time ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of all banks of ? 0.5 ? 0.25 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 0.5 ? 0.35 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 0.9 ? 0.75 ns packages at same power supply voltage, temperature, package type and speed grade c l = 30pf f 67mhz (see figure 3) fct807bt fct807ct symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay 1.5 3.8 1.5 3.5 ns t phl t r output rise time ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of all banks of ? 0.5 ? 0.35 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 0.6 ? 0.45 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 1 ? 0.75 ns packages at same power supply voltage, temperature, package type and speed grade c l = 30pf f 40mhz (see figure 4)
5 idt74fct807bt/ct fast cmos 1-to-10 clock driver commercial and industrial temperature ranges notes: 1. see test circuits and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. t plh , t phl , t sk (t) are production tested. all other parameters guaranteed but not production tested. 4. propagation delay range indicated by min. and max. limit is due to v cc , operating temperature and process parameters. these propagation delay limits do not imply skew. switching characteristics over operating range - industrial (3,4) fct807bt fct807ct symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay 1.3 2.9 1.3 2.7 ns t phl t r output rise time ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of all banks of ? 0.6 ? 0.35 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 0.6 ? 0.45 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 0.9 ? 0.65 ns packages at same power supply voltage, temperature, package type and speed grade 50 ? to v cc /2, c l = 10pf (see figure 1) or 50 ? ac termination, c l = 10pf (see figure 2) f 100mhz outputs connected in groups of two fct807bt fct807ct symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay 1.5 4 1.5 3.7 ns t phl t r output rise time ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of all banks of ? 0.6 ? 0.35 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 0.6 ? 0.45 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 0.9 ? 0.75 ns packages at same power supply voltage, temperature, package type and speed grade c l = 30pf f 67mhz (see figure 3) fct807bt fct807ct symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay 1.5 4 1.5 3.7 ns t phl t r output rise time ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of all banks of ? 0.6 ? 0.45 ns same package (inputs tied together) t sk(p) pulse skew: skew between opposite transitions ? 0.7 ? 0.55 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 1 ? 0.75 ns packages at same power supply voltage, temperature, package type and speed grade c l = 30pf f 40mhz (see figure 4)
6 commercial and industrial temperature ranges idt74fct807bt/ct fast cmos 1-to-10 clock driver pulse generator r t d.u.t. v cc v in c v out l 50pf pulse generator r t d.u.t. v cc v in v out c l 30pf pulse generator r t d.u.t. v cc v in v out 50 10pf 220pf pulse generator r t d.u.t. v cc v in v out 100 100 10pf v cc pulse generator r t d.u.t. v cc v in c l v out 50pf 500 500 7.0v the capacitor value for ac termination is determined by the operating frequency. for very low frequencies a higher capacitor value should be selected. test circuits fig. 5: enable and disable time circuit definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. test switch disable low 6v enable low disable high gnd enable high switch position fig. 1: 50 ? ? ? ? ? to v cc /2, c l = 10pf fig. 2: 50 ? ? ? ? ? ac termination, c l = 10pf fig. 3: c l = 30pf circuit fig. 4: c l = 50pf circuit
7 idt74fct807bt/ct fast cmos 1-to-10 clock driver commercial and industrial temperature ranges t plh1 output 1 output 2 t sk(o) t plh2 3v 0v v oh 1.5v 1.5v v ol v oh 1.5v v ol input t phl1 t phl2 t sk(o) 3v 0v v oh t plh t phl v ol 1.5v 1.5v t r t f 2.0v 0.8v input t plh1 package 1 output package 2 output t sk(t) t plh2 3v 0v v oh 1.5v 1.5v v ol v oh 1.5v v ol t phl1 t phl2 t sk(t) control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable t sk(o) = |t plh2 - t plh1 | or |t phl2 - t phl1 | t plh t phl 3v 0v v oh 1.5v 1.5v v ol t sk(p) = |t phl - t plh | t sk(t) = |t plh2 - t plh1 | or |t phl2 - t phl1 | input output input output v ol v oh test waveforms package delay pulse skew - t sk(p) enable and disable times output skew - t sk(o) part-to-part skew - t sk(t) notes: 1. diagram shown for input control enable-low and input control disable-high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns note: 1. package 1 and package 2 are same device type and speed grade.
8 commercial and industrial temperature ranges idt74fct807bt/ct fast cmos 1-to-10 clock driver ordering information 1-to-10 clock driver idt74fct xxxx device type x package so sog py pyg q qg 807bt 807ct small outline ic soic - green shrink small outline ic ssop - green quarter-size small outline ic qsop - green x temp. range blank i commercial (0c to +70c) industrial (-40c to +85c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
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